Basics of I2C protocol:

Brief description:

I2C communication bus has two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device connected to the has the unique address. The devices connected to the bus are recognizes as master or slave. A master initiates the data transfer on the bus, and generates clock for data transfer. the device which is addressed by the master in referred as slave. I2C is multi-master bus, as it allows more than one connected device to control the bus.

Refer below image for terminologies in I2C.

Example of I2C bus configuration:

SDA and SCL signals:

Both SDA and SCL are bidirectional lines, connected to a positive supply voltage pull-up resistor. when the bus is free both SDA and SCL line are pulled high. Output stages of devices have wired AND configuration, which will help in bus arbitration and clock synchronization.

Data validity:

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH 

or LOW state of the data line can only change when the clock signal on the SCL line is 

LOW. 

START and STOP conditions:

All transactions begin with a START (S) and are terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In 

this respect, the START (S) and repeated START (Sr) conditions are functionally identical. 

Byte format:

Every byte put on the SDA line must be eight bits long. The number of bytes that can be 

transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge 

bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

Acknowledge (ACK) and Not Acknowledge (NACK):

ACK is when transmitter releases SDA line in the acknowledgement clock pulse, and then receiver can pull the SDA line low, and it remains low during high period of this clock.

NACK is when SDA remains HIGH during this ninth clock pulse.

The master can then generate either a STOP condition to abort the 

transfer, or a repeated START condition to start a new transfer. There are five conditions 

that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to 

respond with an acknowledge.

2. The receiver is unable to receive or transmit because it is performing some real-time 

function and is not ready to start communication with the master.

3. During the transfer, the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver must signal the end of the transfer to the slave transmitter.

Clock synchronization:

Two masters can begin transmitting on a free bus at the same time and there must be a
method for deciding which takes control of the bus and complete its transmission. This is
done by clock synchronization and arbitration. In single master systems, clock synchronization and arbitration are not needed.

Clock synchronization is performed using the wired-AND connection of I2C interfaces to
the SCL line. The wired-AND property of SCL means that a device that first generates a low period on SCL (device #1) overrules the other devices. At this high-to-low transition, the clock generators of the other devices are forced to start their own low period. The SCL is held low by the device with the longest low period. The other devices that finish their low periods must wait for SCL to be released, before starting their high periods. A synchronized signal on SCL is obtained, where the slowest device determines the length of the low period and the fastest device determines the length of the high period.

 Arbitration:

If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration

procedure is invoked. The arbitration procedure uses the data presented on the serial data bus (SDA) by

the competing transmitters. 

The first master-transmitter, which drives SDA high, is overruled by another master-transmitter that drives SDA low.The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value. Should two or more devices send identical first bytes, arbitration continues on the

subsequent bytes. If the I2C module is the losing master, it switches to the slave-receiver mode, sets the arbitration lost (AL) flag, and generates the arbitration-lost interrupt. If during a serial transfer the arbitration procedure is still in progress when a repeated START condition or a STOP condition is transmitted to SDA, the master-transmitters involved must send the repeated START condition or the STOP condition at the same position in the format frame. Arbitration is not allowed between:

• A repeated START condition and a data bit

• A STOP condition and a data bit

• A repeated START condition and a STOP condition

Courtesy: TI & NXP.

Thank you!.

SPI vs I2C:

1. I2C is quite involved, supporting multiple masters on the bus. Which causes significant overhead in the bus protocol, an ACK for every byte and intentional delays to arbitrate access to the bus. Also a set maximum bus rate, 100 kHz in the original spec, 400 kHz is common today, additional 10 kHz low-speed and 3.4 Mhz high-speed modes, the 2012 spec defines a 5 Mhz ultra-fast mode.

    SPI is much simpler, a single master with no bus protocol beyond a chip select and no set maximum bus rate. If the distances are short then you can go as fast as you dare. Quite fast on an interconnect between chips that are less than an inch apart.

2. I2C: all lines are open-collector which means that the transmitter only drives the line low. When the transmitter releases the line, a resistor connected to Vcc (supply voltage) pulls the light high. However, due to capacitance of the wire and the components, the wire goes to high voltage relatively slowly. Because of this, the clock speed must be reduced to allow time for the lines to "drift" high.

    SPI: all lines are driven by the transmitter both high and low. This minimizes the time required for the wire to change states.

3. SPI is full deplex and I2C is half duplex.

4. I2C require less pin then SPI (SPI 3wire: 3 IOs, SPI 4 wire: 4 IOs, I2C: 2 IOs) as SPI require slave select for individual device.

Note: To save pins used when having multiple slaves in the system, Daisy-Chaining concept is used. read more here.

5.  SPI is faster than I2C.

Basics of SPI protocol:

Serial Peripheral Interface:

Common serial interface on many microcontrollers

 Simple 8-bit exchange between two devices

 Master initiates transfer and generates clock signal

 Slave device selected by master

 One-byte at a time transfer

 Data protocols are defined by application

 Must be in agreement across devices

SPI Block Diagram:

 8-bits transferred in each direction every time

 Master generates clock

 MOSI: “Master Out Slave In”; MISO: “Master In Slave Out”

 Connect MOSI to MOSI and MISO to MISO

 Very clean terminology, unlike “TX” and “RX” which are easy to confuse

 Slave Select (SS) used to select one of many slaves

 Terminology varies:

 Instead of SS, “Chip Select” (CS)

 Instead of MOSI and MISO, SIMOD and SOMI

Using SPI as a bus:

Configuration details to watch out for:

 CPHA (Clock PHase) aka ~CKPH (MSP430 terminology)

 = 0 or =1, determines when data goes on bus relative to clock

 CPOL (Clock POLarity) aka CKPL (MSP430)

 =0

 clock idles low between transfers

 =1

 clock idles high between transfers

This leads to 4 SPI clock modes

SPI timing diagram:

SPI properties:

 Pros

 Simplest way to connect 1 peripheral to a micro

 Fast (10s of Mbits/s, not on MSP) because all lines 

actively driven, unlike I2C

 Clock does not need to be precise

 Nice for connecting 1 slave

 Cons

 No built-in acknowledgement of data

 Not very good for multiple slaves

 Requires 4 wires

 3 wire variants exist…some get rid of full duplex and share a 

data line, some get rid of slave select.